Field of the Invention
The invention relates in general to a signal processing system, a signal processing chip and a signal processing method, and more particularly to a video signal processing system, a video signal processing chip and a video signal processing method.
Description of the Related Art
As display panel technologies continue to progress, the size of display devices is also ever-increasing. A large-sized display device is capable of more precise displays to present better image quality.
For a display device having high resolution, dual video signal processing chips are needed for processing video signal. FIG. 1 shows a schematic diagram of a conventional video signal processing system 9000. The video signal processing system 9000 includes a first video signal processing chip 910, a second video signal processing chip 920, a display card 980, and a display device 990. The first video signal processing chip 910 includes a first controller 911 and a first scaler 912. The display card 980 outputs a first video signal S91 and a second video signal S92. For example, the first video signal S91 is a signal of a left-half image, and the second video signal S92 is a signal of a right-half image.
After the first video signal S91 is inputted into the first scaler 912, the first scaler 912 adjusts the first video signal S91 to a first processed video signal S91′ according information of the display device 990 such as image ratio and resolution.
The first controller 911 receives an information inspection signal S93 from the first scaler 912 to determine whether the first video signal S91 is stable. After the first controller 911 determines that the first video signal S91 is in a stable state, the first controller 911 outputs a notification signal S95 to the first scaler 912 to notify the first scaler 912 to output the first processed video signal S91′ to the display device 990.
Similarly, after the second video signal S92 is inputted into the second scaler 922, the second scaler 922 adjusts the second video signal S92 to a second processed video signal S92′ according to the information of the display device 990 such as image ratio and resolution.
The second controller 921 receives an information inspection signal S94 from the second scaler 922 to determine whether the second video signal S92 is stable. After the second controller 921 determines that the second video signal S92 is in a stable state, the second controller 921 outputs a notification signal S96 to the second scaler 922 to notify the second scaler 922 to output the second processed signal S92′ to the display device 990.
However, time points at which the first controller 911 determines that the first video signal S91 is in a stable state and the second controller 921 determines that the second video signal S92 is in a stable state may not be the same time point, in a way that the image displayed by the display device 990 may appear asynchronously. Thus, there is a need for overcoming such bottleneck for video signal synchronization in the field of dual video signal processing chips.